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特征

· VDD1 = 1.8V (1.7V to 1.95V)
· VDD2, VDDCA and VDDQ = 1.1V (1.06 to 1.17)
· VSSQ terminated DQ signals (DQ, DQS_t, DQS_c, DMI)
· Single data rate architecture for command and address;
- all control and address latched at rising edge of the clock
· Double data rate architecture for data Bus;
- two data accesses per clock cycle
· Differential clock inputs (CK_t, CK_c)
· Bi-directional differential data strobe (DQS_t, DQS_c)
- Source synchronous data transaction aligned to bi-directional differential data strobe (DQS_t, DQS_c)
· DMI pin support for write data masking and DBIdc functionality
· Programmable RL (Read Latency) and WL (Write Latency)
· Burst length: 16 (default), 32 and On-the-fly
- On the fly mode is enabled by MRS
· Auto refresh and self refresh supported
· All bank auto refresh and directed per bank auto refresh supported
· Auto TCSR (Temperature Compensated Self Refresh)
· PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask
· Background ZQ Calibration

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